Specifications

Doc Number: VIS-ANA-VER-01001-9002
Date: 27 May 2004
Issue: 5.0
Page: 65 of 80
Author: J. Delgadillo
Controls Preliminary Design Report Issue 5.doc
Below are the initial break frequencies that we will start-off with the integrated testing at
Mexia, Texas.
AZ ALT
LAG 1 0.0 Hz 0.0 Hz
Lead 0.24 Hz 0.192 Hz
Crossover 1.00 Hz 0.80 Hz
Lag 2 10.00 Hz 10.00 Hz
The single PI architecture that the LCU’s Position Loop will implement is compatible with
the MCU position loop architecture, with the exception of the absence of the LAG2 break
shown on the Bode plot. VertexRSI will implement an active (hardware) low pass filter that
will be added to the LCU rate command output so that the LCU position loop will be
completely compatible with the MCU’s. During the Integrated testing at Mexia, Texas, the
optimal position loop compensation needed will be determined. VertexRSI will do a
mapping of the optimal MCU position loop parameters to the ESO PI compensation loop
parameters. In this manner, during the VPO testing period, the LCU can test the mount
performance using the same Position Loop filtering that the MCU used for initial sell-off the
Mount Control System.
The major subassemblies that make up the MCU are listed below:
MANUFACTURER MANUFACTURER
PART NUMBER
DESCRIPTION
Antron SP2-4300FB MCU Power Supply
Shuttle Computer Group G7VP2 MCU Motherboard
NEC Electronics NL6448AC33-29 LCD Display
Touchstone Technology ASM5051 LCD Controller Board
Chinon America Inc. FZ-357 Floppy Drive
M-Systems Inc. IDE-FD25-32 Hard Drive
Following are some of the MCU Modes of Operation and a brief description of each.