Specifications

How to Manage VHDL Design Hierarchies
VHDL Reference Manual 6-9
Work is the default name of the current library. The work library is
where, in a simulation system, all of your design units (entities,
architectures, packages, and configurations) will be placed after they
are analyzed, unless you have specified an alternate (named) library.
Unlike simulation environments, the VHDL synthesizer only considers
design units that are currently being compiled (those in the current
source file) to be in the work library. This means that the VHDL
synthesizer will not be able to access design units (such as packages)
that are located in another source file using the work library.
The Dataio and Generics Libraries
In addition to the ieee and std libraries, two custom libraries, dataio
and generics, are provided with the VHDL synthesizer. These libraries
(which are provided in source file form in the lib5 installation
subdirectory, and in simulation compiled form in the generic/vhdl
subdirectory) are used for type conversions and for simulation of
generic symbols, respectively. Examples of using these libraries can be
found in the tutorials chapter of the VHDL Entry manual.
Using Schematics With VHDL
The Project Navigator allows schematic and VHDL sources to be
intermixed in an arbitrary hierarchy. When such a design is entered,
there are certain rules that you must follow to ensure that the design
is able to be simulated (using the VHDL simulator) and properly
synthesized.
Note: Although VHDL is case-insensitive, the VHDL synthesizer
preserves the case (upper- and lower-case characters) used in all
VHDL signal names. Because some device-specific fitting software is
sensitive to case (and will not, for example, recognize that two signals
named Reset and RESET are the same), you should be careful to use
consistent signal names in different parts of your design. This is
particularly true when combining schematics with VHDL; always check
to make sure that the signal names used on the schematic match
properly with the names used in VHDL portions of the design.
Using A Top-Level Schematic With VHDL
You can create designs that are a mixture of top-level schematic files
and lower-level VHDL files, but there are a few rules that you must
observe:
• Use std_logic or std_logic_vector data types as interfaces
between blocks on the schematic and lower-level VHDL design
entities. When installed, the schematic VHDL netlist writer is set up
(via .INI files settings) for this data type, and will make reference
to lower-level design units using std_logic and std_logic_vector
as appropriate. If necessary, use the type conversion functions
provided in the dataio library (/lib5/dataio.vhd) to convert non-
std_logic data types to std_logic within the VHDL design units.