Specifications

How to Manage VHDL Design Hierarchies
VHDL Reference Manual 6-7
Using Packages For Common Declarations
To define common declarations (such as types, subtypes or
subprograms), you may want to use a package that is shared between
different VHDL sources files. Although this is quite easy to do in
simulation systems (you simply all of the source files, including the file
containing the package, into work and place appropriate use
statements before each design unit requiring the package), there are
some restrictions on how you can do this using the VHDL synthesizer.
If you need to reference a package from within two or more different
source files (for example, from your actual design description and from
a test bench, or from two or more source files referenced in the
hierarchy of the design), you must place the package declaration in a
separate VHDL source file and reference it as a named library. You do
this by referencing the external source file containing the package in
each of the source files using library statements. During synthesis,
the VHDL synthesizer will include the external source file containing
the package declaration into the files that contain the library
statements. During simulation, you must compile the external source
file containing the package into an appropriately named library before
compiling the higher-level source files. For example, if you have the
following package:
library ieee;
use ieee.std_logic_1164.all;
package typedef is
subtype byte is std_logic_vector (7 downto 0);
end;
and you wish to reference the type byte in more than one source file
in your design, then you must place the package in a unique source
file, and place library statements prior to the entity declarations in all
source files that require the byte data type:
library mytypes;
use mytypes.typedef.all;
In this use statement, mytypes corresponds to the name of the
external VHDL source file containing the package (in this case,
mytypes.vhd). During synthesis, the VHDL synthesizer will include the
mytypes.vhd file each time it encounters the library statement. When
you simulate the design, you will compile the mytypes.vhd file into a
named library (mytypes) prior to compiling the other source files into
the work library.
For more information on these and other uses of packages and
libraries, refer to a standard VHDL text.