Specifications

How to Manage VHDL Design Hierarchies
VHDL Reference Manual 6-3
In this example, the architecture of addmult contains a declaration of
two components, add and mult, and one instance of each component.
The three design entities are arranged in the hierarchy shown in
Figure 6-1.
Figure 6-1: Hierarchy of the Addmult Multiplexer
Hierarchical designs contain multiple design entities, and may be
written using more than one source file, or by entering multiple design
entities (entity/architecture pairs) in the same source file.
Components And Synthesis
Using components to partition a large design can have advantages for
synthesis. Many of the optimizations performed by the VHDL
synthesizer operator at the component level, meaning that a design
written using components can process more efficiently. Large designs
can create very long run times during synthesis, so breaking up the
design into smaller pieces using components is recommended. In
addition to performing logic optimizations at the level of components,
the VHDL synthesizer will detect multiple references to (instances of) a
component, and will not attempt to perform the same optimizations
twice for the same circuitry. The synthesizer will instead make a copy
of the already-optimized circuitry to create the additional instances.
Using Multiple Hierarchical VHDL Files
If you use multiple VHDL source files to describe the hierarchy of your
design, and have entered only a single entity/architecture pair in each
VHDL file, then the Project Navigator will determine the hierarchy of
your design for you, and will display the VHDL sources as a hierarchy
(by indenting them in the Sources Window). When the design is
synthesized, the Project Navigator runs the VHDL synthesizer once for
each source file. During synthesis, hierarchy references are be
generated for each VHDL file. After synthesis, the synthesized logic for
each module is combined (by linking or merging) during the device
fitting process.
Note: The point at which a hierarchical design is linked or merged
depends on the type of device selected. Designs being implemented in
PLD-type devices are linked prior to the device fitting process, while
designs being implemented in FPGA devices are merged later, during
the fitting process. For FPGA devices, partitioning a large design into
multiple source files can greatly reduce the processing time required
for the design.