Specifications

VHDL Reference Manual 6-1
6. How to Manage VHDL
Design Hierarchies
Managing Large Designs
This section shows you how to use partitioning and design
management to manage larger designs. The VHDL constructs for
partitioning and sharing code modules are the component,
configuration, block and library statements. You should refer to a
standard VHDL reference text for detailed descriptions of these
partitioning statements. In this section, methods for design
partitioning that are most relevant to synthesis will be discussed.
Additional methods of design partitioning, using packages, will be
discussed in the section that follows.
Hierarchy
Hierarchy is a way of managing a design by creating references to
external, lower-level design modules (entities) from within a higher-
level design module. The concept of hierarchy in VHDL is similar to the
concept of hierarchy as implemented in many schematic entry
systems. The basic unit of hierarchy in VHDL is the component. A
component is a VHDL entity that is referenced as a lower-level module
from another, higher-level entity.
A VHDL entity can have multiple architectures, and a particular
entity/architecture pair (referred to as a design entity) can be
referenced from another architecture as a VHDL component.
Instantiating components within another design provides a mechanism
for partitioned designs, or for using existing designs as reusable
components of larger designs.
You can manage the relationship between a component declaration
and various design entities by using configuration specifications.
Configuration statements are supported in the VHDL synthesizer, and
are described later in this chapter. There are default configurations, so
it usually not necessary to include configuration specifications in your
designs.