Specifications

VHDL Datapath Synthesis
5-14 VHDL Reference Manual
G_ROM
At the current time G_ROM is never inferred. It may be instantiated,
but is only supported for Altera targets, where it maps directly to the
Altera LPM_ROM macro. See the Altera MaxPlus documentation for
details.
Functional Simulation
Functional simulation models for the Synario generic datapath
macrofunctions are supplied in the file
<SYNARIO>\generic\vhdl\gen_dpe.vhd. This file will automatically be
compile into the appropriate library in the Vsystem simulator if you
following the instructions outlined in the SYN-VHDL ReadMe.
Note that at the current time, the following limitations apply with
respect to these models:
1. Models for the G_RAM_DQ and G_ROM do not support loading their
initial contents from a data file. To load these memories with initial
values during simulation, use the FORCE command in Vsystem.
2. All models only support a value of UNSIGNED for the
REPRESENTATION generic.