Specifications

VHDL Datapath Synthesis
VHDL Reference Manual 5-13
G_MULT
The following table describes the ports of the G_MULT:
Port Usage Default
Value
Description Comments
Dataa Required None First data input Size equals WIDTHA generic.
Datab Required None Second data input Size equals WIDTHB generic.
Sum Optional Logic 0 Partial Sum. Size equals WIDTHS generic.
Product Optional None Product output. Product = Dataa * Datab +
Sum. Size equals WIDTHP
generic.
Notes:
1. Most targets do not support the Sum port.
G_MULT also has the following generics:
Generic Usage Description Comments
Widtha Required The width, in bits, of the Dataa
port.
Must be an integer value >= 2.
Widthb Required The width, in bits, of the Datab
port.
Must be an integer value >= 2.
Widths Required The width, in bits, of the Sum
port.
Must be an integer value >= 2.
Widthp Required The width, in bits, of the Product
port.
Must be an integer value >= 2.
Representation Required Indicates whether UNSIGNED or
SIGNED math is to be
performed.
Only the value UNSIGNED is
currently supported.
An example of an instantiated G_MULT is:
i_mult0: g_mult
generic map(widtha=>4, widthb=>4, widthp=>8,
representation => "unsigned")
port map(dataa=>din0, datab=>din1, product=>mult_out);
G_RAM_DQ
At the current time G_RAM_DQ is never inferred. It may be
instantiated, but is only supported for Altera targets, where it maps
directly to the Altera LPM_RAM_DQ macro. See the Altera MaxPlus
documentation for details.