Specifications

VHDL Datapath Synthesis
5-12 VHDL Reference Manual
G_COUNTER also has the following generics:
Generic Usage Description Comments
Width Required The width, in bits, of the Dataa,
Datab, and Sum ports.
Must be an integer value >= 2.
Representation Required Indicates whether UNSIGNED or
SIGNED math is to be
performed.
Only the value UNSIGNED is
currently supported.
Modulus Optional The terminal count of the
counter.
If not set, terminal count will
default to 2**WIDTH - 1.
Avalue Optional Value loaded by the Aconst
input.
See Note 2., above.
Svalue Optional Value loaded by the Sconst
input.
See Note 2., above.
Pvalue Optional Power-up value of the Q output. For simulation, defaults to 0.
Notes:
1. Most targets do not support Modulus, Avalue, and Svalue.
2. At the current time no targets support Pvalue. With the default
value for this generic, the Q output of the functional simulation
model will initialize to 0. This may or may not match the behavior
of the target implementation.
An example of an instantiated G_COUNTER is:
i_count0: g_counter
generic map (width=>16, REPRESENTATION => "UNSIGNED")
port map (data=>din0, clock=>clock, aclr=>areset, sload=>sload,
q=>count_out);