Specifications

VHDL Datapath Synthesis
5-10 VHDL Reference Manual
i_addsub0: g_add_sub
generic map (width => 8, representation => "UNSIGNED")
port map(dataa=>din0, datab=>din1, sum=>add_sub_out);
Note that the REPRESENTATION generic must be assigned a valid
value, even though it is defined to have default value in the
component declaration. This is true for all datapath macrofunctions.
G_COMPARE
The following table describes the ports of the G_COMPARE:
Port Usage Default
Value
Description Comments
Dataa Required None First data input Size equals WIDTH generic.
Datab Required None Second data input Size equals WIDTH generic.
Alb Optional None High if Dataa < Datab Not(Alb) = Dataa >= Datab
Aeb Optional None High if Dataa = Datab Not(Aeb) = Dataa /= Datab
Agb Optional None High if Dataa > Datab Not(Agb) = Dataa <= Datab
G_COMPARE also has the following generics:
Generic Usage Description Comments
Width Required The width, in bits, of the Dataa,
Datab, and Sum ports.
Must be an integer value >= 2.
Representation Required Indicates whether UNSIGNED or
SIGNED math is to be
performed.
Only the value UNSIGNED is
currently supported.
An example of an instantiated G_COMPARE is:
i_compare0: g_compare
generic map (width => 8, representation => "UNSIGNED")
port map(dataa=>din0, datab=>din1, alb=>a_lt_b, aeb=>a_eq_b,
agb=>a_gt_b);
G_COUNTER
The following table describes the ports of the G_COUNTER:
Port Usage Default
Value
Description Comments
Data Optional None Data input Size equals WIDTH generic.
Clock Required None Clock input Rising edge sensitive clock
input.
Enable Optional Logic 1 Active high clock enable Defaults to enabled.
Updown Optional Logic 1 Up/down counter control Counter counts up when high,
counts down when low. Defaults