Specifications

VHDL Datapath Synthesis
5-8 VHDL Reference Manual
Resource Sharing
Consider the following simple ALU:
p0: process(operand0, operand1, operand2, opcode)
begin
case(opcode)
when ADD_OPERAND1 =>
result <= operand0 + operand1;
when SUB_OPERAND1 =>
result <= operand0 - operand1;
when ADD_OPERAND2 =>
result <= operand0 + operand2;
when others =>
result <= operand0 - operand2;
end case;
end process;
Because resource sharing is not currently supported, this code will
infer 4 different ADD_SUB macros. A better approach would be to
instantiate a single ADD_SUB, and generate the inputs to it from a
process:
p0: process(opcode)
begin
case(opcode)
when ADD_OPERAND1 =>
add_sub <= '1';
b <= operand1;
when SUB_OPERAND1 =>
add_sub <= '0';
b <= operand1;
when ADD_OPERAND2 =>
add_sub <= '1';
b <= operand2;
when others =>
add_sub <= '0';
b <= operand2;
end case;
end process;
p1: add_sub
generic map (width => 8, representation => "UNSIGNED")
port map(dataa => operand0, datab => b, add_sub => add_sub, sum =>
result);
Essentially, you should separate datapath from control logic,
instantiating the datapath and leaving the control logic for synthesis.