Specifications

VHDL Datapath Synthesis
VHDL Reference Manual 5-7
Inferencing Details
This section provides additional details on inferencing.
Supported Types
Inferencing is supported for operands of type bit_vector,
std_logic_vector, IEEE unsigned, and integer. If you are synthesizing
designs originally developed in the Synopsys environment, the type
unsigned in the package stdarith.std_logic_arith may also be used.
In general, integer is a poor choice. The reason for this can be seen by
examining the following code fragment, which will infer an ADD_SUB:
signal a, b, c: integer range 0 to 255;
c <= a + b;
For situations where the sum of a+b is greater than 255, a fatal
assertion will occur during simulation. This is different than the
behavior of an actual ADD_SUB macro, which will rollover when the
sum is greater than 255.
The behavior of code written using the overloaded arithmetic operators
supplied in either the dataio.std_logic_ops package (for
std_logic_vector) or in the IEEE package numeric_std (for types
unsigned and signed) will mimic the behavior of the LPM
macrofunctions that are inferred, and therefore we recommend the use
of these types.
Matching Semantics
In order for datapath macrofunctions to be inferred, the simulation
semantics of VHDL code must match the semantics of the
corresponding macrofunction. For example:
process(clk)
begin
if (rising_edge(clk)) then
if (load = '1') then
a <= b;
elsif (clk_en = '1') then
a <= a + 1;
end if;
end if;
end process;
would not infer COUNTER. The reason for this is that the clock enable
input to an LPM COUNTER must override the load input, and this is not
the case for the code fragment shown.