Specifications

VHDL Datapath Synthesis
VHDL Reference Manual 5-5
COUNTER
Inference of the COUNTER macro works very similarly to that for the
ADD_SUB. Examples of code that will infer counters are:
signal a : std_logic_vector(3 downto 0) := (others => '0');
p0: process(clk)
begin
if (rising_edge(clk)) then
a <= a + '1';
end if;
end process;
signal c : std_logic_vector(7 downto 0) := (others => '1');
p1: process(clk, my_async_ctrl)
begin
if (my_async_ctrl = '0') then
c <= (others => '1');
elsif (rising_edge(clk)) then
if (my_state = load_state) then
c <= b;
else
c <= c + 1;
end if;
end if;
end process;
Process p0 infers a simple COUNTER with only the Clock and Q ports
connected. The initial state of signal a during simulation would be
"UUUU", and this code would fail to count properly except that we have
used an initial assignment on the declaration of signal a. If you use a
default assignment like this to get proper simulation behavior, be sure
that your choice of a default value matches the register power-up state
in your target device, otherwise mismatches will occur between the
functional and timing simulations and your device will not work as
intended.
Process p1 infers a COUNTER configured as an up counter with a low-
active asynchronous preset and synchronous load. Note that here we
are assuming that our registers will power-up to the logic 1 state.