Specifications

VHDL Datapath Synthesis
5-2 VHDL Reference Manual
How Inferencing Works
Inferencing is currently supported for the following macros:
♦ ADD_SUB
♦ MULT
♦ COUNTER
♦ COMPARE
Inferencing is performed based upon a combination of the operators
(+, -, >, etc.) that appear in your VHDL code and the context in which
those operators appear. For example,
signal a, b, c: std_logic_vector(7 downto 0);
c <= a + b;
would infer an ADD_SUB configured to perform addition.
Similarly, the code
signal clk : std_logic;
signal a : std_logic_vector(7 downto 0);
process(clk)
begin
if (rising_edge(clk)) then
a <= a + 1;
end if;
end process;
would infer an 8 bit COUNTER.
In both of these examples, the overloaded operator '+' is used, but the
context is different.
Controlling Datapath Inferencing
The inferencing feature of Synario’s VHDL compiler is automatically
enabled if you are targeting a device where this feature is supported.
You may disable it by changing the properties for Synthesize Logic.
To disable inferencing :
1. In the Sources list in Project Navigator, click once to highlight a
VHDL source file.
2. In the Processes list, highlight the Synthesize Logic process.
3. Click the Properties button.
4. Set the LPM Inferencing property to False.
To enable inferencing for certain source files and not for others, use
Synario’s Strategy feature. This feature allows you to associate one or
more source files in your design with a particular synthesis and
optimization “style”. See “Strategies” in the Synario online help for
more information on using the Strategy feature.