Specifications

VHDL Reference Manual 5-1
5. VHDL Datapath Synthesis
A common problem with using VHDL synthesis for FPGA and PLD
design is that synthesis tools often to a relatively poor job of
implementing datapath logic (wide adders, counters, multipliers, and
the like). There are a number of potential reasons for this:
• Datapath functions such as adders have many different potential
implementations, all representing different speed/density trade-
offs.
• Many FPGA and PLD vendors offer optimized libraries of datapath
functions, designed for efficient implementation in their specific
architecture.
• Synthesis tools to break all logic down to the level of Boolean
equations so that datapath functions are no longer recognizable as
such.
In order to avoid the efficiency issues that crop up when datapath
functions are decomposed into Boolean equations, Synario’s VHDL
synthesis compiler has the ability to infer the use of certain common
datapath functions from your VHDL code and extract them from your
design. This inferencing capability is based on the LPM (Library of
Parameterized Modules) Specification, which is simply a industry-
standard set of variable-width macrofunctions such as adders,
counters, etc. After these macrofunctions are extracted from your
design they are mapped to a specific implementation based upon the
chosen target device.
LPM inferencing from VHDL is currently supported for three Synario
Device Kits; Actel, Altera, and Actel. For Xilinx designers, a similiar
capability is available through the X-BLOX standard, consult the LCA
Device Kit manual for details.
There are two ways to take advantage of Synario’s datapath synthesis
and mapping capability in your VHDL designs:
♦ Allow Synario’s VHDL compiler to infer the use of LPM
macrofunctions from “generic” VHDL code that you write.
♦ Instantiate macrofunctions from Synario’s Generic Datapath
(gen_dp) library.