Specifications

How to Control the Implementation of VHDL
4-12 VHDL Reference Manual
Using IEEE 1076.3 Unsigned/Signed Types
In late 1995 the IEEE 1076.3 commitee approved a new VHDL package called
numeric_std. This package defines two vector types, unsigned and signed, and
the appropriate overloaded operators for these types. Both unsigned and signed
are based upon the std_logic type. This has several implications:
• You can not assign a signal of type std_logic_vector to one of type unsigned
(or signed) or visa-versa. For example:
signal slv : std_logic_vector(3 downto 0);
signal uns : unsigned(3 downto 0);
.
.
slv <= uns;
will not compile.
• Since the post-route netlists produced for VHDL simulation are usually
defined in terms of std_logic and std_logic_vector, is is impossible to "plug in"
a post-route netlist into a testbench in place of a functional design that had
ports of type unsigned or signed.
For these reasons, it is recommended that types unsigned/signed only be used in
places where the overloaded functions defined in the numeric_std package are
needed. Explicit type conversions can be performed at the point of use, for
example:
signal a,b,z : std_logic_vector(3 downto 0);
.
.
z <= std_logic_vector(unsigned(a) + unsigned(b));
In this code fragment, the vectors a and b are converted to unsigned, summed
using the overloaded '+' operator defined by numeric_std, and the result is then
converted back to a std_logic_vector type before being assigned to z. If you
prefer to use unsigned/signed throughout your design, it is suggested that you still
make your top-level inputs and outputs type std_logic_vector, and convert them in
your top level module before using them throughout the rest of your design.