Specifications

How to Control the Implementation of VHDL
4-10 VHDL Reference Manual
Selecting a Base Data Type
An important consideration when starting a VHDL design project is the
data type upon which your design is to be based. Typically, you will
use one of the following types:
• Integer
• Bit and bit_vector
• Std_ulogic and std_ulogic_vector
• Std_logic and std_logic_vector
• Std_logic and the unsigned/signed data types defined by IEEE
1076.3
The default type for wires and pins in Synario's schematic editor is std_logic (or
std_logic_vector for busses). If you wish to use a different type on schematics,
you must either change the net_type and bus_type settings in the
\synario\config\vhdl.ini file, or change the type of individual wires and buses by
setting the VHDL_NetType VHDL_BusType attribute on the schematic. Refer to
the Netlist Application Note available through online help for details.
The advantages and disadvantages of designing using different base types is
discussed below.
Using the Integer Type
Using an integer type has the advantage that all the normal
arithmetic operators are built into the VHDL language for this type.
Another advantage of using integers is that they use memory
efficiently during simulation. To understand why this is so, consider
the following declarations:
signal a_int : integer range 0 to 255;
signal a_vec : bit_vector(7 downto 0);
Both a_int and a_vec are capable of representing exactly the same
range of values. Note that the declaration of a_int defines one signal,
while the declaration of a_vec really defines eight signals (one per bit
of the vector). To support attributes, there is a variety of information
that a VHDL simulator must store for each signal (such as the last
value, whether the signal is active or not, and so on), so using an
integer is more efficient.
There are several disadvantages to using integers, however. The first
is that there is no way for an integer to represent several common
logic states such as unknown, tristate, or don’t-care. The second
problem is that when writing VHDL code that performs integer
operations, you must include extra code to check for boundary
conditions. Consider the following code fragment:
signal a, b, z : integer range 0 to 7;
z <= a + b;