Specifications

How to Control the Implementation of VHDL
4-8 VHDL Reference Manual
Controlling Feedback Paths
If the design description specifies feedback, then the VHDL synthesizer
will generate the feedback logic according to how the fed back signal
was used in the design. There are two basic types of feedback
generated from the VHDL synthesizer: macrocell (register) feedback
and pin feedback. The source of the feedback (register or pin) may be
controlled by using appropriate VHDL coding conventions.
If a port of type inout is both read from and written to, (as is the case
for bi-directional I/O) then the pin feedback path is generated. If the
specified port is written to only and the feedback is assigned to a
signal, the register feedback is generated. A port that is both read and
written must be of mode inout, and a port that is written to only may
be either out or inout.
For example, consider two implementations of a 3-bit counter. The first
counter uses the register feedback path, and the second uses the pin
feedback path.
In the first case, the counter is specified by a variable named count1,
and the output of the counter drives the pin count. This describes
register feedback, since the value is fed back with the variable
count1.
entity counter0 is
port (clock: in Boolean;
count: out integer range 0 to 7);
end counter0;
architecture register_feedback of counter0 is
begin
process (clock)
variable count1: integer range 0 to 7;
begin
if clock and clock'event then
if count1 = 7 then
count1 := 0;
else
count1 := count1 + 1;
end if;
end if;
count <= count1;
end process;
end register_feedback;
In the second case, the counter is described directly with the port
count. Note that count is now an inout so that it may be read from
and written to. The counter feedback uses the VHDL port directly, and
will therefore result in the pin feedback path being generated.