Specifications

How to Control the Implementation of VHDL
VHDL Reference Manual 4-7
o1,o2: out std_logic);
end polarity;
architecture inversion of polarity is
signal n2: std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
o1 <= (a and b);
n2 <= (not a or not b);
end if;
end process;
o2 <= not n2;
end inversion;