Specifications

How to Control the Implementation of VHDL
4-6 VHDL Reference Manual
Controlling Output Inversion
Many common PLDs feature inverted registered outputs, or outputs
that have programmable inverters between the outputs of the flip-flops
and the actual output pins. When designing for these devices, precise
control over the polarity of the outputs is often required. Using
properties of the VHDL synthesizer, you have three options available
for controlling output polarities.
If the target device has outputs with fixed output inversion on all
registered outputs, then the Invert Yes property of the Synthesize
VHDL process should be specified when compiling your design. The
Invert Yes property results in all registered ports in the design being
generated with inverted outputs. This option does not affect the logic
of the outputs as observed on the pins; instead it simply instructs the
VHDL synthesizer to change the inversion of the output pins, then
invert the internal logic polarity (and swap presets and resets as
needed) to preserve the correct pin-to-pin behavior of the circuit.
If the target device has outputs with fixed non-inverted registered
outputs, then you should specify Invert No when processing your
design. This property results in all design outputs being generated with
non-inverting outputs. Once again, the logic of the circuit as observed
in the device output pins remains unaffected, regardless of how the
outputs are described in the VHDL program.
If the target device features programmable output inversion for
registered outputs (as is the case in the P22V10 and the smaller MACH
devices) then you can either select Invert Yes or Invert No, or do not
specify the inversion and let the VHDL synthesizer choose the output
inversion based on how the outputs are used in the design description.
If the Invert property is not specified, the VHDL synthesizer attempts
to infer the inversion of outputs based on the use of inverting signals
in the design.
Note: Most PLD Device Kits include a flip-flop transformation process
that can adjust output polarities to match the architecture of the target
device. For this reason, you will probably not have to use the Invert
Yes or Invert No property to achieve a successful fit.
The following example shows two design outputs. The o2 output is
described in such a way that it will result in inverted outputs (using a
variable to provide the inversion) while the o1 output is described in a
way that will result in a non-inverted implementation. (Both o1 and
o2 have the same pin-to-pin behavior.)
library ieee;
use ieee.std_logic_1164.all;
entity polarity is
port (clock : in std_logic;
a,b: in std_logic;