Specifications

How to Control the Implementation of VHDL
4-2 VHDL Reference Manual
The type std_ulogic (from which std_logic is derived) is also an
enumerated type, and has the definition (from ieee.vhd):
type std_ulogic is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
The std_ulogic (or std_logic) data type is very important for both
simulation and synthesis. Std_logic includes values that allow you to
accurately simulate such circuit conditions as unknowns and high-
impedance states. For synthesis purposes, the high-impedance and
don’t-care values provide a convenient and easily recognizable way to
represent three-state enables and don’t-care logic.
Synthesis of Enumerated Types
When synthesized into logic, enumerated types result in a binary
encoding. Elements in the enumerated type are assigned numeric
values from left to right, with the value of the leftmost element being
zero. For example, the state values defined earlier would be assigned
the binary values 00, 01, 10, and 11 for the states st0, st1, st2 and
st3, respectively.
If the number of elements in the enumerated type is not a power of 2
(for example, there are only three states, instead of four), the
remaining binary encodings are processed as don’t-cares by the VHDL
synthesizer.
The default (binary) encoding for enumerated types is rarely the
optimal encoding for a complex state machine, so it is important to
have a way to override the default with an encoding more appropriate
for the machine being described. The default binary encoding can be
changed if needed, using the enum_encoding attribute that will be
described in this section.
By default, the number of wires generated to encode an enumerated
type is the smallest possible n, where the number of elements is 2
n
.
(It will, for example, require three wires to represent an enumerated
type with more than four but less than nine different values.) The
enum_encoding attribute allows you to specify no only the encoding of
each member of the type, but the width of the encoding (number of
wires) as well.
Enum_encoding attribute
The VHDL synthesizer supports a custom synthesis attribute for objects
of enumerated types that allows alternate encodings to be specified.
An alternate encoding may be required for a state machine that is
described with enumerated types, or may be required to resolve multi-
valued logic into a single-bit representation.