Specifications

How to Write Synthesizable VHDL
3-32 VHDL Reference Manual
Perhaps the most common mistake made by new VHDL users
(particularly those who have had experience with PLD-oriented
languages) is in assuming that unspecified conditions will have no
effect on the logic of the generated circuit. This is not the case in
VHDL, and you need to be aware of the logic that will be generated for
incompletely specified conditions.
To help you detect and correct situations such as this, the VHDL
synthesizer will display a warning message whenever asynchronous
feedback paths are generated. (You can view these warning messages
by viewing the Process Log in the Project Navigator.)