Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-31
Mealy state machines can be written more clearly, however, if three
processes are used in the following style:
architecture mealy of system is
signal C: std_logic;
signal B: std_logic;
begin
Registers: process (clock) -- State register
begin
if rising_edge(clock) then
C <= B;
end if;
end process;
Transitions: process (A, C) -- Transition logic
begin
B <= F1(A, C);
end process;
Outputs: process (A,C) -- Mealy outputs
begin
D <= F2(A, C);
end process;
end mealy;
Figure 3-9 shows a block diagram of this type of state machine. The
block labeled F1 represents the combination logic function for the
transition logic, while the block labeled F2 represents a combinational
logic function of the state machine’s current state and the design
inputs.
Figure 3-9: Mealy State Machine
Avoiding Unwanted Latches
When describing state machines in VHDL, you must be careful to avoid
the creation of unwanted asynchronous feedback paths that form
latches. The rules of VHDL state that a signal within a process whose
value is not completely specified (provided with an explicit assignment
for all possible input conditions) will hold its previous value for the
unspecified conditions. Latches can therefore be inadvertently created
by incompletely specifying the transitions from one or more states in a
state machine, or by failing to specify the value of all outputs in the
states of the machine.