Specifications

How to Write Synthesizable VHDL
3-30 VHDL Reference Manual
Input Registers
If the system timing requires no logic between the registers and the
input (a short setup time is required) the following architecture can be
used:
architecture moore4 of system is
signal A1, D1 : std_logic;
begin
Registers: process (clock)
begin
if rising_edge(clock) then
A1 <= A;
D1 <= D;
end if;
end process;
F1: process (A1, D1)
begin
D <= F(A1,D1);
end process;
end moore4;
The resulting circuitry is diagrammed in Figure 3-8. Note that this
form of a state machine does not map well into most PLD devices.
Figure 3-8: Moore4 State Machine
Mealy Machine
A Mealy machine always requires two processes (or one process for
the machine and separate concurrent statements for the outputs,) as
its timing is a function of both the clock and the data inputs:
architecture mealy of system is
signal C: std_logic;
begin
Combinational: process (A,C) -- Mealy outputs
begin
D <= F2(A, C);
end process;
Registers: process (clock) -- State machine logic
begin
if rising_edge(clock) then
C <= F1(A, C);
end if;
end process;
end mealy;