Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-29
A more compact description of this architecture could be written as
follows:
architecture moore2 of system is
signal C: std_logic;
begin
Combinational: process (C) -- combinational -logic
begin
D <= F2(C);
end process;
Registers: process (clock) -- sequential logic
begin
if rising_edge(clock) then
C <= F1(A, C);
end if;
end process;
end moore2;
Output Registers
If the system timing requires that there be no logic between the
registers and the output (the shortest output propagation delay is
desired) then the following architecture can be used:
architecture moore3 of system is
begin
process (clock)
begin
if rising_edge(clock) then
D <= F(A,D)
end if;
end process;
end moore3;
This is the simplest form of a Moore state machine, and is diagrammed
in Figure 3-7.
Figure 3-7: Moore3 State Machine