Specifications

How to Write Synthesizable VHDL

3-26 VHDL Reference Manual

This state machine description includes two combinational outputs

(port comb_outputs) that decode the current state of the machine. If

these outputs were registered, rather than combinational, then a third

process would have been written for the outputs, using the clk and

reset inputs in the process sensitivity list.

Note: Methods for specifying the encoding of enumerated types, and

the impact that these types have on optimization results, are described

later in this chapter in the section, "Enumerated Types".

Feedback Mechanisms

All state machines require some form of feedback to implement the

current state memory and next state decoding. There are two ways to

create feedback in VHDL: using signals and using variables. The

recommended method for state machines is to use signals, as shown in

the previous template example.

Note: As a general rule, use variables to pass data within a process,

and use signals to pass data outside a process (between concurrent

statements).

Feedback on Signals

The following design demonstrates how signals are used to provide

to provide the clocking function for the flip-flop. The flip-flop output (c)

is fed back and used in the assignment of combinational signal b in the

second process:

architecture example of some_entity is

signal b: bit;

begin

process(clk) -- a sequential process

begin

if clk = '1' and clk'event then -- clock function

if reset = '1' then

c <= '0'; -- synchronous reset

else

c <= b; -- load flip-flop from b

end if;

end process;

process (a, c) -- a combinational process

begin

b <= a and c;

end process;

end example;

When relating this circuit to a classic state machine, you can consider

the signal c to the current state register, and signal b to the next state

decode function.

For simple state machine circuits such as this one (or for somewhat

more complex circuits such as counters), a more concise method of

specifying the feedback can be used: