Specifications

How to Write Synthesizable VHDL
3-22 VHDL Reference Manual
Synchronous Set/Reset
To add the behavior of synchronous set or reset you can simply add a
conditional assignment to a constant value immediately inside the
clock specification. This is a VHDL coding convention that is recognized
as a hardware reset by the VHDL synthesizer. Other methods of reset
control may have the desired behavior, but do not result in a hardware
reset feature being utilized.
The following example shows a simple preset of a 1-bit (Boolean)
output:
process(clk)
begin
if clk='1' and clk'event then
if set='1' then
y <= '1';
else
y <= a and b;
end if;
end if;
end process;
The example sets y to true when the set input is high during a rising
clock edge.
The next example shows how a constant value can be specified to
reset the output to an arbitrary encoding. When this example is
processed by VHDL, a mixture of reset and preset features is utilized to
create the desired reset output encoding:
process (clk)
begin
if clk='1' and clk'event then
if init='1' then
y <= 7; -- y is type integer
else
y <= a + b;
end if;
end if;
end process;
Note: If the target device supports only a reset feature and does not
have a preset feature, then you can use the Generate Reset Logic
property of the VHDL synthesizer to ensure that only resets are
generated.
Asynchronous Set/Reset
To describe the behavior of asynchronous set or reset, the initialization
is no longer within the control of the clock. Instead, simply add a
conditional assignment to a constant immediately outside the clock
specification. Because the outputs must change asynchronously when
the reset input is high, the reset input must be included in the
sensitivity list of the process:
process (clk,reset)
begin
if reset='1' then
y <= false; -- y is type Boolean