Specifications

How to Write Synthesizable VHDL
3-20 VHDL Reference Manual
Example 1:
A process statement for a flip-flop is identical to the first latch
example, above, with addition of the 'event attribute to specify an
edge. The sensitivity list for the process contains only the clock input,
since the output of a flip-flop only changes when the clock transitions
from low to high:
process (clk)
begin
if clk='1' and clk'event then
y <= a and b;
end if;
end process; -- A Process statement :
Example 2:
This example shows how to use a wait statement to describe a flip-
flop. When a wait statement is used, there is no sensitivity list
associated with the process statement. To accurately describe an edge
triggered flip-flop on the output, the wait statement must be the first
statement in the process:
process
begin
wait until clk'event and clk='1'; -- rising edge
y <= a and b;
end process;
Example 3:
This example uses a procedure declaration, and is identical to the
second latch example, above. The only difference is the addition of the
'event attribute to define the clock as an edge triggered signal:
architecture dataflow of flipflop is
procedure my_ff(signal clk,a,b: Boolean;
signal y : out Boolean)
begin
if clk='1' and clk'event then
y <= a and b;
end if;
end;
begin
ff_1: my_ff (clock,input1,input2,outputA);
ff_2: my_ff (clock,input1,input2,outputB);
end dataflow;
Example 4:
This example shows how to use a concurrent conditional assignment to
describe the flip-flop:
architecture concurrent of my_register is
begin
y <= a and b when clk='1' and clk'event;
end concurrent;