Specifications

How to Write Synthesizable VHDL
3-16 VHDL Reference Manual
process(clk)
begin
if clk='1' then
y <= a;
else
y <= b;
end if;
end process;
Note: This example would result in an error during synthesis; because
the conditional logic is completely specified using an else statement,
the process describes a combinational function. The signals a and b are
both inputs to the combinational function, and are therefore required
to be in the sensitivity list.
This convention can be summarized: if an if statement is not
completely specified, then a flip-flop or latch primitive is implied.
Incompletely specified assignments within case statements can also
result in latches being generated, but these latches are constructed
using combinational feedback rather than latch primitives. If the if
statement is completely specified (using an else clause), a
combinational function is implied. There is no significance to any of the
signal names used in these or any other examples. The clock input (in
this case clk) can have any name. Implied flip-flops and latches can
occur on either signals or variables.