Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-15
Describing Sequential Logic
This section describes in detail how various kinds of registered
sequential circuits can be described using VHDL, and how these
descriptions are synthesized into actual circuitry (using latches and
flip-flops).
Describing sequential logic in VHDL is very much like programming in
a conventional programming language, and less like programming
using a traditional PLD programming language. There is no register
assignment operator and no special attributes or “dot extensions” for
specifying clocks and resets. In VHDL, you must describe the behavior
of a sequential logic element such as a latch or flip-flop, as well as
specifying the behavior of more complex sequential machines.
The behavior of a sequential logic element (latch or flip-flop) is to save
a value of a signal over time. This section shows how such behavior
may be described. This description is extended to add the behavior of
set and reset (in both their synchronous and asynchronous forms).
There are often several ways to describe a particular behavior, and the
following examples typically show only two of the many possible
styles. There is no “right” style, however. Your choice of style should
simply be that which helps you specify the clearest description of your
design.
Note: If you deviate from commonly-used VHDL coding conventions
(styles) such as those described in this manual, then you may risk
creating designs that are not portable to other synthesis tools.
There are two commonly-used methods used to describe registered
behavior: conditional (if-then) specifications and wait statements.
Conditional Specification
Describing sequential logic with a conditional specification relies on the
inherent behavior of a VHDL if statement. The convention used for
conditional statements that describe clocking logic is:
process (clk)
begin
if clk='1' then
y <= a;
else
-- default: holds previous value
end if;
end process;
This set of statements describes the behavior of a latch; if the clock is
high the output (y) gets a new value. If the clock is not high then the
output retains its previous value. This is unlike a PLD programming
language such as ABEL-HDL, where the else condition results in the
signal going to zero. If both conditions had been written as
assignments, then the behavior would be that of a mux: