Specifications

Table of Contents
iv VHDL Reference Manual
Describing Combinational Logic...................................................3-2
Constants and Types ............................................................3-3
Logical Operators .................................................................3-3
Relational Operators .............................................................3-5
Arithmetic Operators ............................................................3-6
Shift Operators ....................................................................3-8
Describing Conditional Logic .......................................................3-8
Concurrent Statement: Conditional Signal Assignment..............3-9
Concurrent Statement: Selected Signal Assignment..................3-9
If Statement........................................................................3-9
Case Statement ................................................................. 3-10
Describing Replicated Logic ...................................................... 3-11
Functions and Procedures.................................................... 3-11
Loop Statements ................................................................ 3-12
Generate Statements.......................................................... 3-13
Describing Sequential Logic ...................................................... 3-15
Conditional Specification ..................................................... 3-15
Wait Statement.................................................................. 3-18
Latches ............................................................................. 3-19
Flip-flops........................................................................... 3-19
Gated Clocks and Clock Enable............................................. 3-21
Synchronous Set/Reset ....................................................... 3-22
Asynchronous Set/Reset...................................................... 3-22
Asynchronous Reset/Preset.................................................. 3-23
Describing Finite State Machines ............................................... 3-24
Template State Machine...................................................... 3-25
Feedback Mechanisms......................................................... 3-26
Types of State Machines...................................................... 3-28
Moore Machine................................................................... 3-28
Mealy Machine ................................................................... 3-30
Avoiding Unwanted Latches ................................................. 3-31
4. How to Control the Implementation of VHDL............................................ 4-1
Using Enumerated Types............................................................4-1
A Review of Enumerated Types ..............................................4-1
Synthesis of Enumerated Types .............................................4-2
Enum_encoding attribute ......................................................4-2
“One hot” Enumeration .........................................................4-4
Don’t-cares and Enumerated Types ........................................4-4
Describing Output Enables..........................................................4-5
Using Std_logic to Describe Output Enables.............................4-5
Controlling Output Inversion.......................................................4-6
Controlling Feedback Paths.........................................................4-8