Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-13
While statements are also supported by the VHDL synthesizer, with
the constraint that the loop termination depend only on a value that
can be determined at the time of synthesis (for example, a metalogic
value. See Appendix B, “Limitations,” for more information about
metalogic values).
The following example demonstrates the use of a while loop:
entity while_stmt is
port (a: in bit_vector (0 to 3);
m: out bit_vector (0 to 3));
end while_stmt;
architecture example of while_stmt is
begin
process (a)
variable b: bit;
variable i: integer;
begin
i := 0;
while i < 4 loop
b := a(3-i) and b;
m(i) <= b;
end loop;
end process;
end example;
Unconstrained loops (such "while true" loops) are not supported in
synthesis.
Example schematics for the loop and subprogram are shown in Figure
3-5.
Generate Statements
Generate statements are used to replicate one or more concurrent
statement. The generate statement has two forms: for and if.
For Generation Statement
Following is an example of a for generation statement:
Gen1: for i in 0 to 3 generate
SM: mod1 port map(A(i),B(i),Y(i));
end generate Gen1;
When processed, this statement expands into four statements as
follows:
SM(0): mod1 port map(A(0),B(0),Y(0));
SM(1): mod1 port map(A(1),B(1),Y(1));
SM(2): mod1 port map(A(2),B(2),Y(2));
SM(3): mod1 port map(A(3),B(3),Y(3));
If Generation Statement
The if generation statement is used to describe a conditional selection
of concurrent statements: