Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-11
Describing Replicated Logic
VHDL provides the following subprograms and looping constructs for
creating replicated logic:
• Function
• Procedure
• Loop Statement
• Generate Statement
Functions and procedures are collectively referred to as
subprograms. Generate is a concurrent loop statement. These
constructs are synthesized to produce logic that is replicated once for
each subprogram call, or once for each iteration of a loop.
Functions and Procedures
Functions are always terminated by a return statement, which returns
a value. A return statement may also be used in a procedure, where it
never returns a value.
The following example illustrates the use of a function:
entity func is
port (a: in bit_vector (0 to 2);
m: out bit_vector (0 to 2));
end func;
architecture example of func is
function simple (w, x, y: bit) return bit is
begin
return (w and x) or y;
end;
begin
process (a)
begin
m(0) <= simple(a(0), a(1), a(2));
m(1) <= simple(a(2), a(0), a(1));
m(2) <= simple(a(1), a(2), a(0));
end process;
end example;