Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-9
Concurrent Statement: Conditional Signal Assignment
The following is an example of a conditional signal assignment:
entity control_stmts is
port (a, b, c: in Boolean; m: out Boolean);
end control_stmts;
architecture example of control_stmts is
begin
m <= b when a else c;
end example;
Note: In IEEE standard 1076-1993, the else clause is optional. If you
do not provide an else clause, however, the resulting circuit will
probably include a latch, which may not be the desired result.
Concurrent Statement: Selected Signal Assignment
A selected signal assignment uses the with statement, and must
include all possible cases. The others case ensures that all cases are
covered.
The following is an example of a selected signal assignment:
entity control_stmts is
port (sel: bit_vector (0 to 1); a,b,c,d: bit;
m: out bit);
end control_stmts;
architecture example of control_stmts is
begin
with sel select
m <= c when b"00",
m <= d when b"01",
m <= a when b"10",
m <= b when others;
end example;
If Statement
The condition in an if statement must evaluate to true or false (a
Boolean type). The following example illustrates the if statement:
entity control_stmts is
port (a, b, c: in Boolean; m: out Boolean);
end control_stmts;
architecture example of control_stmts is
begin
process (a, b, c)
variable n: Boolean;
begin
if a then
n := b;
else
n := c;
end if;
m <= n;