Specifications

How to Write Synthesizable VHDL
3-8 VHDL Reference Manual
Shift Operators
The shift operators in VHDL are defined for the types bit and boolean.
In addition, the package std_logic_ops found in the file
\synario\lib5\dataio.vhd supplies overloaded operators for type
std_logic_vector. The left-hand argument of these operators must be
an array type (such as bit_vector or std_logic_vector) and the right-
hand argument must be an integer. The return value is always of the
same type as the left-hand argument. The operators are listed in
Table 3-3.
Table 3-3: Shift Operators
Operator Description
sll Shift Left Logical
srl Shift Right Logical
sla Shift Left Arithmetic
sra Shift Right Arithmetic
rol Rotate Left Logical
ror Rotate Right Logical
The shift operators are not expensive to implement if the right operand
(which must be an integer type) is a constant value. If the right
operand is not a constant (and depends on a signal) then the logic can
be quite expensive to implement.
Describing Conditional Logic
Conditional logic is combinational logic that implements a multiplexer-
like function.
The two forms of concurrent statements used to describe conditional
logic are:
• Conditional signal assignment
• Selected signal assignment
There are also two forms of sequential statements for describing
conditional logic:
• If statement
• Case statement
These statements are discussed individually below.