Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-7
The absolute (abs) operator is not expensive to implement. The **
operator is only supported when its arguments are constants.
The following example illustrates the logic generated for an addition
operation:
package example_arithmetic is
type small_int is range 0 to 7;
end example_arithmetic;
use work.example_arithmetic.all;
entity arithmetic is
port (a, b: in small_int; c: out small_int);
end arithmetic;
architecture example of arithmetic is
begin
c <= a + b;
end example;
Figure 3-3 shows the logic generated for this example in schematic
form. Again, this logic may be collapsed into a sum-of-products (2-
level) form during processing by the VHDL synthesizer and device
fitting.
Figure 3-3: Arithmetic Operators