Specifications

How to Write Synthesizable VHDL
3-4 VHDL Reference Manual
m <= (a and b) or e; --concurrent signal assignments
e <= c xor d;
end example;
Example 2:
entity logical_ops_2 is
port (a, b: in bit_vector (0 to 3);
m: out bit_vector (0 to 3));
end logical_ops_2;
architecture example of logical_ops_2 is
begin
m <= a and b;
end example;
Figure 3-1 shows how these examples are implemented in logic. In
the first example, notice that the logic is shown in a multilevel
implementation. In the logic actually generated, the logic for m will be
a large sum-of-products function with the exclusive-or function (signal
e) expanded into and/or logic and preserved (in a multilevel logic
structure) or flattened into a larger two-level sum-of-products
representation. The actual form of logic generated will depend on the
optimization options chosen in the Project Navigator.
The second example shows how bit_vectors are expanded and
processed. The and operation is distributed through the bit_vector
data for m, as you would expect.
Figure 3-1: Logical Operators