Specifications

VHDL Reference Manual iii
Table of Contents
1. Introduction ................................................................................................. 1-1
2. Language Structure .................................................................................... 2-1
Structure of a VHDL Design Description........................................2-2
Library Units.............................................................................2-3
Package ..............................................................................2-3
Entity .................................................................................2-4
Architecture.........................................................................2-5
Configuration.......................................................................2-5
Statements ..............................................................................2-6
Declaration Statements.........................................................2-6
Concurrent and Sequential Statements ...................................2-6
Data Objects.............................................................................2-8
Variables.............................................................................2-8
Constants............................................................................2-9
Signals ...............................................................................2-9
Data Types............................................................................. 2-11
Numeric Types................................................................... 2-12
Other Types....................................................................... 2-13
Enumerated Types.............................................................. 2-13
The Std_ulogic and Std_logic Data Types .............................. 2-14
User Defined Types and Subtypes ........................................ 2-14
Types and Logic Synthesis................................................... 2-15
Type Conversions ............................................................... 2-15
Operators............................................................................... 2-16
Logical Operators ............................................................... 2-16
Relational Operators ........................................................... 2-16
Arithmetic Operators .......................................................... 2-17
Overloading Operators ........................................................ 2-17
VHDL Attributes ...................................................................... 2-17
3. How to Write Synthesizable VHDL............................................................. 3-1