Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-3
Constants and Types
The context in which an operator is used effects the generated
circuitry. Using constant values or simple one-bit data types results in
the most compact circuitry, while complex data types (such as arrays)
in an expression result in correspondingly more circuitry.
If one operand of a combinational expression is a constant, then less
logic is generated. If both operands are constants, the logic can be
collapsed during compilation and the cost of the operation is zero
gates. Using constants wherever possible means that the design
description will not contain unwanted functionality, will synthesize
faster and produce a more efficient implementation.
Certain operators in VHDL are restricted to specific types, generally
following the programming language conventions which are given in
the following subsections. These subsections describe the following
kinds of operators:
• Logical Operators
• Relational Operators
• Arithmetic Operators
Logical Operators
VHDL provides the following logical operators:
and
or
nand
nor
xor
not
These operators are defined for the types bit and Boolean, and for
one-dimensional arrays of these types (for example, an array of type
bit_vector). These operators are also defined for the IEEE 1164
std_logic (or std_ulogic), and std_logic_vector data types (if the
ieee library and std_logic_1164 package are included in your
design). The generation of logic from language constructs is
reasonably direct, and results in an implementation in gates as shown
in the following two examples.
Example 1:
entity logical_ops_1 is
port (a, b, c, d: in bit; m: out bit);
end logical_ops_1;
architecture example of logical_ops_1 is
signal e: bit;
begin