Specifications

How to Write Synthesizable VHDL
3-2 VHDL Reference Manual
In addition, a VHDL design written for simulation may use enumerated
types to represent the encoding of a group of wires, perhaps as part of
a symbolic state machine description. A design may also use
enumerated types to represent the electrical characteristics on a signal
wire (such as high impedance, resistive, or strong). In this case, the
VHDL synthesizer has no way to distinguish the meaning (in terms of
how the values should be represented in hardware) of each circuit.
Unless you have provided an encoding for these types (using the VHDL
synthesis custom attribute enum_encoding described in this
chapter), the VHDL synthesizer must assume a default encoding for all
enumerated types.
Optimization Strategies
Most, but not all, PLDs are constructed with an input logic array (the
and array) and output register macrocells that are fed by an or gate.
These devices are optimized for wide sum-of-products logic functions.
The macrocells in these devices typically include three-state buffers
and one or more possible feedback paths back into the array. Most
FPGAs, on the other hand, are constructed with smaller basic logic
elements (such as 4- or 5-input lookup tables, or multiplexers). The
VHDL synthesizer, and other processes invoked by the Project
Navigator, include a number of options (properties) that can be
modified to optimize the design for the target device architecture. In
most cases, the default property values (which are set depending on
the device you have selected) will result in the most efficient
implementation. If you want to experiment with different optimization
properties, refer to the on-line help for information about each of the
available properties.
Note: An example of modifying VHDL Synthesis and Design Fitting
properties can be found in in the Craps Game example, in the tutorials
chapter of the VHDL Entry manual.
Describing Combinational Logic
This section describes the relationship between basic VHDL statements
and the resulting synthesized combinational logic. Most of the
operators and statements that are used to describe combinational logic
are the same as found in any programming language. As in a
programming language, some operations take more time (path delays)
to execute in hardware, and some require more space (in this case,
device resources) to implement. Some VHDL operations are more
expensive to synthesize into logic than others because they require
more gates to implement. This section describes the relative costs
associated with various combinational operations, and the kind of
circuitry you can expect to get out of synthesis.