Specifications

VHDL Reference Manual 3-1
3. How to Write
Synthesizable VHDL
The hardware implementation of a design written in VHDL depends on
many factors. Coding conventions, fitter technology, and optimization
options are all factors. The general nature of a design also has a large
impact on its suitability for synthesis to a particular device,
independent of the method used to describe the design.
Not all designs can be synthesized. Many VHDL designs (which are
often referred to as models for simulation) are not suitable for
synthesis. These include high level performance models;
environmental models (test benches) for stimulus/response; or system
models that include a mixture of software, hardware, and physical
aspects. For the purposes of logic synthesis, the VHDL synthesizer
must assume that the entire VHDL design describes digital logic that is
to be implemented in hardware.
Hardware design — and design for synthesis in particular — adds
several additional constraints that must be considered above and
beyond the requirements for simulation. One example of this is a gated
clock . A gated clock may not be an issue for simulation, since values
may be written to a computer’s memory without concern for electrical
glitches. When designing for synthesis, however, care must be taken
to ensure that the circuit described will actually control the clocking of
memory elements in a manner appropriate for the target hardware.
A simulation model may also describe the timing characteristics of a
design. Timing specifications (such as inertial or transport delays) are
ignored by the VHDL synthesizer, and the actual timing behavior of the
design depends on the architecture and mapping of the target device.
For this reason, a VHDL model that depends on the timing for correct
operation may not synthesize to the expected result when moved from
one target device to another.
Simulation models may describe unbounded conditions (such as loops
that have no termination, or integers that have no range) that are
impossible represent in hardware. In some cases (such as infinite
loops) the synthesis tool will produce an error and exit, while in other
cases (such as unbounded integers) the VHDL synthesizer will assume
a default representation (for example, 32 bits), which may or may not
result in the expected circuit being generated.