Specifications

Language Structure
2-16 VHDL Reference Manual
if clk = '1' and clk'event then
p <= To_Vector(2,To_Integer(p) + 1);
end if;
end process;
end behavior;
The example shown makes use of the package std_logic_ops in the
dataio library provided with the VHDL synthesizer. This library includes
commonly-used type conversion functions (such as To_Integer and
To_Vector).
Operators
VHDL includes the following kinds of operators:
• Logical
• Relational
• Arithmetic
Logical Operators
Logical operators, when combined with signals and/or variables, are
used to create combinational logic. VHDL provides the following logical
operators:
and
or
nand
nor
xor
not
These operators are defined for the types bit , std_ulogic (which is the
base type of std_logic) and Boolean, and for one-dimensional arrays
of these types (for example, an array of type bit_vector or
std_logic_vector).
Relational Operators
Relational operators are used to create equality or magnitude
comparison functions. VHDL provides the following relational
operators:
= Equal to
/= Not equal to
> Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to
The equality operators ( = and /= ) are defined for all VHDL data
types. The magnitude operators ( >=, <=, >, < ) are defined for
numeric types, enumerated types, and some arrays. The resulting type
for all these operators is Boolean.