Specifications

Language Structure
2-10 VHDL Reference Manual
Like initial values, delays specified using the optional after keyword
are ignored by the synthesis compiler, since it has no way of
guaranteeing that a particular delay will occur in the target hardware.
Therefore, you will not normally use the after clause when writing
code for synthesis. However, it is important to realize that even
without an after clause, all signal assignments occur with some
infinitesimal delay, known as delta delay. Technically, delta delay is of
no measurable unit, but from a hardware design perspective you
should think of delta delay as being the smallest time unit you could
measure, such as a femtosecond.
The effect of delta delay on the simulation behavior of your code can
be profound. Consider the following example. Assume that the signal
first_sig is assigned the value 11 at time 100 ns:
first_sig <= 11;
first_sig actually changes to its new value 1 fs after time 100 ns. Now
consider the next two assignments executed at time 200 ns:
first_sig <= 25;
first_var := first_sig;
If both of these assignments are executed at time 200 ns, first_var
immediately takes on the value 11, and 1 fs later first_sig has the
value 25.