Specifications

Language Structure
VHDL Reference Manual 2-9
In these assignments, the variable named first_var is being assigned
an integer value of 45 (For more information on data types, including
integer, see the next section). A variable named SECOND_VAR is then
assigned to whatever value first_var currently contains, which is 45.
SECOND_VAR is then assigned the integer value 0. The variables
named second_var and SECOND_VAR are the same, since VHDL is not
case-sensitive.
Note: In VHDL, names (or identifiers, as they are more properly
referred to) must begin with a letter, and may consist of any number
of letters, digits, or underscores, as long as there is not more than one
underscore in a row. As noted earlier, no distinction is made between
upper- and lower-case characters.
Before they can be used, variables must be declared with a variable
declaration statement, as in the following example:
variable first_var : integer;
variable second_var, third_var : integer := 0;
A variable declaration begins with the keyword variable, followed by
one or more names, the data type, and optionally, an initial value.
Variables may be declared only within processes or functions, two
constructs that are explained later in this chapter.
Constants
Constants are much like variables, except, as they name implies, their
value can never change. Constants are normally employed to make
code easier to read and to modify.
Like variables, constants are declared with a declaration statements.
An example of a constant declaration is as follows:
constant one_grand : integer := 1000;
Signals
Signals are declared in much the same manner as variables. Signal
declarations may include an initial value, which will be ignored by the
synthesis compiler. Examples of signal declarations are as follows:
signal first_sig : integer;
signal second_sig, third_sig : integer := 5;
Signal assignments are performed using the <= operator, as in the
following examples:
first_sig <= 9;
second_sig <= first_sig;
third_sig <= first_sig after 5 ns;
The first clue as to the fundamental difference between signals and
variables is found in the assignment to third_sig. The example
specifies that third_sig will take on the value held by first_sig, but with
a delay of 5 nanoseconds. This is in essence propagation delay.