Specifications

Language Structure
2-8 VHDL Reference Manual
architecture behavior of some_thing is
begin
process begin
wait until clock;
if (accelerator = '1') then
case speed is
when stop => speed <= slow;
when slow => speed <= medium;
when medium => speed <= fast;
when fast => speed <= fast;
end case;
end if;
end process;
end behavior;
Note: Sequential statements do not imply, and are not the same as,
sequential logic.
Data Objects
Data objects hold values. Languages such as C and Pascal generally
have only one type of data object: the variable. In addition to the
variable, VHDL has two other types of data objects: constants and
signals. VHDL variables work in much the same way as variables in
conventional programming languages. From a hardware designer’s
perspective, both signals and variables can be thought of as wires
interconnected with various logic gates. The differences among VHDL
data objects lay in how they may be used and how much information
they contain.
Before they can be used, data objects must be declared with a
declaration statement, as explained separately for each of the three
data types, below. Note that the VHDL synthesis compiler ignores
initial values on both signals and variables, since most types of
hardware currently available do not have a guaranteed power-up state.
Therefore, when writing VHDL code, it is best not to use initial values
unless you know that you are guaranteed a certain power-up state in
your target device.
Variables
Like a variable in C or Pascal, a variable in VHDL carries with it only
one piece of information: its current value. Variables are assigned a
value using the := operator. Consider the following variable
assignments:
first_var := 45;
SECOND_VAR := first_var;
second_var := 0;