Specifications

Index
Index-6 VHDL Reference Manual
lower-level .............................................................................................. 6-10
top-level ...................................................................................................6-9
using with VHDL.........................................................................................6-9
Selected signal assignment ..................................................................... 3-8, 3-9
Sensitivity ..................................................................................................C-12
Sequential logic .......................................................................................... 3-15
Sequential statement.............................................................................. 2-2, A-3
Shift operators..............................................................................................3-8
signal ........................................................................................................ 3-26
Signal attributes ....................................................................................B-1, C-2
Signals ........................................................................................................2-9
Simple comparisons.......................................................................................3-5
sla...............................................................................................................3-8
sll ...............................................................................................................3-8
sra ..............................................................................................................3-8
srl ...............................................................................................................3-8
State machine ..............................................................................................C-9
Mealy............................................................................................. 3-28, 3-30
Moore ..................................................................................................... 3-28
multiple .................................................................................................. 3-28
template ................................................................................................. 3-25
State machines ........................................................................................... 3-24
encoding ...................................................................................................4-3
one hot .....................................................................................................4-4
PREP4 example ..........................................................................................4-3
Statement
block ........................................................................................................6-1
case................................................................................................. 3-8, 3-10
component ................................................................................................6-1
concurrent.......................................................................................... 2-2, 2-7
exit......................................................................................................... 3-12
if 3-8, 3-15
library.......................................................................................................6-1
next........................................................................................................ 3-12
package ....................................................................................................6-1
procedure................................................................................................ 3-19
return ..................................................................................................... 3-11
sequential ..........................................................................................2-2, A-3
use ...........................................................................................................2-3
wait .........................................................................................3-15, 3-18, B-1
with..........................................................................................................3-9
Statements ..................................................................................................2-6
Std_logic type...............................................................................................4-3
std_logic[std_logic] ..................................................................................... 2-11
std_logic_vector[std_logic_vector] ................................................................ 2-11
Std_ulogic type.............................................................................................4-2
String ........................................................................................................ 2-11
Subprogram .................................................................................................A-4
Subprograms.............................................................................................. 3-11
Subtraction operators ....................................................................................3-7
Subtype declaration......................................................................2-14, 2-15, B-2
Subtypes.................................................................................................... 2-11
Synchronous preset and reset....................................................................... 3-22