Specifications

Language Structure
2-6 VHDL Reference Manual
Statements
There are three basic kinds of statements in VHDL:
Declaration Statements
Concurrent Statements
Sequential Statements
Declaration Statements
Declaration statements are used to define constants (such as literal
numbers or strings), types (such as records and arrays), objects (such
as signals, variables and components), and subprograms (such as
functions and procedures) that will be used in the design. Declarations
can be made in many different locations within a VHDL design,
depending on the desired scope of the item being declared.
Concurrent and Sequential Statements
Concurrent and sequential statements are the fundamental building
blocks of a VHDL design description. These statements, which
represent the actual logic of a design, include such things as signal
assignments, component instantiations, and behavioral descriptions.
There are important distinctions to be made between concurrent and
sequential statements, as discussed below.
Concurrent Statements
Concurrent statements are evaluated independently of the order in
which they appear. A concurrent statement is much like a signal
assignment used in a PLD programming language such as ABEL-HDL.
Signals pass values between concurrent statements, much as wires
connect components on a schematic. The “components” being
connected in a VHDL design might be logical elements that have been
described using concurrent signal assignments, or they might be
instances of lower-level entities.
Concurrent statements define logic (typically in the form of signal
assignments that include combinational logic) that is inherently
parallel. With concurrent statements, values are carried on signals,
which may be the actual input and output ports of the design (defined
in an entity statement) or local signals declared using a signal
declaration statement.