Specifications

How to Control the Implementation of VHDL
D-2 VHDL Reference Manual
Dot extensions
Identifier names used in ABEL-HDL equations may include dot
extensions. Dot extensions provide a means to refer specifically to
internal signals and nodes that are associated with a primary signal in
a design.
Dot extensions are used in complex language constructs, such as
nested sets or complex expressions.
Pin-to-Pin Vs. Detailed Dot Extensions
Dot extensions refer to various circuit elements (such as register
clocks, presets, feedback and output enables) that are related to a
primary signal.
Some dot extensions are general purpose and are used with a wide
variety of device architectures. These dot extensions are therefore
referred to as pin-to-pin (or "architecture-independent"). Other dot
extensions are intended for specific classes of device architectures, or
require specific device configurations. These dot extensions are
referred to as detailed (or "architecture-dependent" or "device-
specific") dot extensions.
Table C-2 lists the ABEL-HDL dot extensions. Pin-to-pin dot
extensions are indicated with a check in the Pin-to-Pin column.
Table C-2: Dot Extensions
Dot
Ext.
Pin-to-
pin
Description
.ACLR ü A device-independent asynchronous register
reset, equivalent to .AR with ISTYPE 'buffer'
(or .AP with ISTYPE 'invert').
.AP Asynchronous register preset
.AR Asynchronous register reset
.ASET ü A device-independent asynchronous register
preset, equivalent to .AP with ISTYPE 'buffer'
(or .AR with ISTYPE 'invert').
.CE Clock-enable input to a gated-clock flip-flop
.CLK1 ü Clock input to an edge-triggered flip-flop
.CLR ü A device-independent synchronous register
reset, equivalent to .SR with ISTYPE 'buffer'.