Specifications

VHDL Reference Manual D-1
D. ABEL-HDL Language
Reference
The information in this appendix is provided to help you read and
interpret the logic equations that the Project Navigator produces in
reports and error messages. These equations use a subset of the ABEL-
HDL equation language to represent the logic of your design. These
equations are produced by most device fitter software, as well as the
equation report generator, which displays the Synthesized, Reduced
and Linked Equations.
The following equation is an example of the ABEL-HDL equation
syntax:
Q0_.D = A & Dir & Sel
# B & !Dir & Sel
# C & Sel;
The equations displayed are in a sum-of-products (2-level) form, and
include the operators shown in Table C-1.
Table C-1: ABEL-HDL Operators
Operator Description
= Assignment
:= Registered Assignment
! Not (invert)
& AND
# OR
$ Exclusive-OR
!$ Exclusive-NOR