Specifications

VHDL for the ABEL-HDL Designer
VHDL Reference Manual C-13
Because IEEE 1164 std_logic_vector data types do not have a '+'
operator defined for them, the counter portion of the design has been
described using an integer data type (the signal Count). A type
conversion function (To_Vector) has been used to convert the integer
data type into a std_logic_vector data type suitable for the design's
output. This type conversion function (and others) is provided in the
dataio library supplied with the VHDL option.