Specifications

VHDL for the ABEL-HDL Designer
VHDL Reference Manual C-11
A Standard ABEL-HDL Design in VHDL
The VHDL source file, cntbuf.vhd, shows how one of the standard
ABEL-HDL examples can be written in VHDL. This example
demonstrates:
• Pin assignments
• Bidirectional I/O
• Output enable conventions
• Synchronous reset logic
The complete VHDL description is listed below.
---------------------------------------------------------
-- VHDL Version of standard ABEL example CNTBUF.ABL
-- Michael Holley, Data I/O Corp.
--
-- Copyright 1994, Data I/O Corporation
--
library ieee;
use ieee.std_logic_1164.all;
entity cntbuf is
port( Dir: in std_logic;
Clk,Clr,OE: in std_logic;
A,B: inout std_logic_vector(0 to 1) bus;
Q: inout std_logic_vector (3 downto 0) bus);
attribute pinnum : string; -- Must define the attribute
attribute pinnum of Clk : signal is "1";
attribute pinnum of Clr : signal is "2";
attribute pinnum of Dir : signal is "3";
attribute pinnum of OE : signal is "11";
attribute pinnum of A : signal is "13,12";--A_0_=3,A_1_=12
attribute pinnum of B : signal is "19,18";--B_0_=19,B_1_=18
attribute pinnum of Q : signal is "17,16,15,14";
end cntbuf;
library dataio;
use dataio.std_logic_ops.To_Vector;
architecture example of cntbuf is
signal Count: integer range 0 to 15;
begin
process (Dir,A,B) -- Bi-directional buffer
begin
if Dir = '1' then
B <= "ZZ"; -- Make B high Z
A <= B;
else
B <= A;
A <= "ZZ"; -- Make A high Z